1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for forming a multilevel contact opening.
2. Description of Related Art
Currently, semiconductor fabrication technology has achieved a deep sub-micron level so that semiconductor devices can be fabricated with a high degree of integration. The trend toward miniaturization, in which integrate circuit devices are designed with a higher and higher degree of integration, continues. In order to achieve a desired degree of integration with low fabrication cost, a multilevel contact etching process should be able to simultaneously etch oxide and Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y, and stop on silicon and silicide. However, a current conventional multilevel contact etching process cannot stop on silicon and silicon nitride at the same time due to a poor etching selectivity between oxide and silicide.
FIG. 1A and FIG. 1B are schematic, cross-sectional views of a portion of a substrate, schematically illustrating a contact opening formed by a conventional multilevel contact etching process. In FIG. 1A, there is a silicon substrate 100. A polysilicon, TiSi.sub.x /poly, or WSi.sub.x /poly layer 110 and a silicide layer 130, such as titanium silicide or tungsten silicide, have been separately formed on the substrate 100. The polysilicon layer 110 can also be a polycide, such as silicide/polysilicon to serve as a main part of a gate. A Si.sub.3 N.sub.4 /SiO.sub.x,N.sub.y, layer 120 is formed on the polysilicon layer 110. A silicon oxide layer 140 is formed over the substrate 100 to cover exposed surfaces of the silicon substrate 100, the polysilicon layer 110, the silicide layer 130, and the Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y layer 120. A photolithography process is performed to define locations on the silicon oxide layer 140 for subsequently forming desired openings. A conventional multilevel contact etching process is performed to etch the silicon oxide layer 140 and the Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y layer 120 so as to simultaneously form contact openings 150, 160, and 170. The contact opening 150 stops at the silicon substrate 100. The contact opening 160 penetrates through the silicon oxide layer 140 and the Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y layer 120 and stops at the polysilicon layer 110. The contact opening 170 stops at the silicide layer 130. In an actual situation, the contact opening 170 enters into the silicide layer 130, or completely removes the silicide layer 130 because of over-etching due to a poor etching selectivity between the silicon oxide layer 140 and the silicide layer 130. As shown in FIG. 1A, this causes the silicide layer 130 to be partially or completely removed during over-etching.
The conventional multilevel contact etching process is performed in a magnetically enhanced reactive ion etching (MERIE) etcher with a plasma gas etchant composed of C.sub.n F.sub.2n+2 /O.sub.2 /CO/Ar. This plasma gas etchant has a trade-off between selectivity of silicon oxide : silicide and silicon oxide : Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y, and a trade-off between selectivity of silicon oxide : silicide and Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y as it is completely removed. When the conventional multilevel contact etching process is etching the Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y layer 120 to expose the polysilicon layer 110, the silicide layer 130 has already been partially or completely removed during over-etching. If the over-etching phenomenon is severe, the silicide layer 130 may be completely etched through. This causes a current leakage in the actual device.
On the other hand, if the contact opening 170 is formed by etching and intended to stop on the silicide layer 130, the contact opening 160 may not be able to extend to the polysilicon layer 110, as shown in FIG. 1 B. A residue of the Si.sub.3 N.sub.4 /SiO.sub.x N.sub.y layer 120 causes a blind contact opening, and an open circuit therefore occurs.